| Summary: | 博士 === 國立交通大學 === 電子工程系 === 91 === The main topics of this thesis can be divided into two categories; (1) low temperature poly-Si TFTs with lightly doped drain structure; (2) low temperature poly-Si TFTs using ICP plasma oxidation gate dielectric layer. The maxima process temperature of device fabrication is 400oC except the amorphous silicon film deposition by LPCVD at 550oC.
At first, two novel fabricating processes, which are used to form the lightly doped drain (LDD) and gate-overlapped lightly doped drain (GOLDD) structures, have been proposed to suppress the lateral electric field in the drain junction and reduce anomalous leakage current. In general, additional mask and n- implantation for the LDD are necessary to form the LDD poly-Si TFTs. Herein, gate oxide of poly-Si TFT is defined and used as implantation mask. Therefore, the source/drain and LDD implantation can be performed in one ion implantation process. The gate oxide thickness and implantation parameters are optimized to form the LDD. Results indicate the poly-Si grain structure in LDD region greatly affects the electrical characteristics of LDD TFTs. After optimizing the process parameters, the On/Off current ratio can be as high as 107 while the field effect mobility slightly decreases. Poly-Si TFTs with LDD structure exhibit better hot carrier stress endurance than conventional self-aligned poly-Si TFTs.
Another proposed LDD structure in this thesis is gate-overlapped lightly doped drain (GOLDD) structure. First, Al gate electrode is isotropic etched to form the LDD region without using additional mask. Thereafter, excimer laser annealing is used to activate dopants in source/drain regions. At the same time, the dopants in source/drain regions laterally diffuse into LDD region to form lightly doped poly-Si without additional ion implantation. Finally, Ni sub-gate is selective and isotropic deposited on Al gate electrode to control the LDD region by Ni electroless plating solution. Poly-Si TFTs with Ni sub-gate overlapped LDD structure exhibit low leakage current, high on current, suppression of kink effect, and good hot carrier stress endurance.
In the study of low temperature poly-Si TFTs with ICP plasma oxidation gate dielectric layer, we first study the influences of ICP process parameters on the electrical characteristics of plasma oxidation oxide. Results show that plasma oxide with 10% oxygen gas flow rate in ICP plasma gas mixtures, Ar+O2, exhibits high breakdown field of 9 MV/cm, low leakage current of <5×10-8 A/cm2 at 8MV/cm, and good interface trap state density of 3╳1011 /eV.cm2 on c-Si substrate. According to the analyses of hydrogen and oxygen depth profiles and grain boundary activation energy evaluated from poly-Si film conductivity, ICP Ar-O2 plasma has passivation effect to the grain boundaries trap states in poly-Si film. In a way, poly-Si TFTs with ICP Ar-O2 plasma gate oxide show good electrical characteristics. The threshold voltage of complementary ICP Ar-O2 TFTs is less than |0.5 V|. Sub-threshold swing is less than 100 mV/dec. Carrier field effect mobility can be as high as 170 cm2/V•s for n-channel device and 80 cm2/V•s for p-channel device. The short-channel effect is not obvious until channel length is less than 4 m.
At final in this thesis, we investigate the stability of ICP Ar-O2 TFTs. The main degradation mechanisms of n-channel device are the large lateral electric field in drain junction resulting in hot carrier degradation and self-heating degradation caused by high driving power of device on poor thermal conductance substrate. Both these degradations will become prominent as the channel length scaling down. In the study of p-channel device stability, electron trapping in the gate oxide near to drain and hole trapping in the gate oxide are the main degradation mechanisms of p-channel TFTs. The bias stress with large electric field in the drain junction induces the impact ionization. The generated electrons inject into gate oxide near to drain and degrade device stability. The hole trapping in the gate oxide is caused by the large |Vgs| bias stress. It results in threshold voltage shift and on current degradation. In general, the influences of hole trapping is more serious than that of electron trapping. he degradations of p-channel TFTs under both stress conditions become severe when the gate length is less than 4m.
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