| Summary: | 博士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === In this dissertation, we will study borderless contact (BLC) process of the silicide and non-silicide technologies for sub-quarter micron ULSI CMOS applications. The characteristics of a new and improved borderless contact (BLC) are studied. A low-temperature and high deposition rate CVD-oxynitride (SiOxNy) film is used to act as the selective etching stop layer. The additional n+ and p+ source-drain double implant structure (DIS) are employed in the studied device. The additional n+ and p+ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. In addition, double ion-implant (DII) Ti-salicide with the arsenic pre-amorphization implantation (PAI) and Si ion-mixing implant have been developed successfully and studied. The DII technique is combined by germanium (or arsenic) PAI and Si ion-mixing implant without additional lithography process. The sheet resistances both of n+ and p+ polysilicon resistors with DII process are decreased especially in the narrow gate width regime. Based on this technology, the good performances of uniform Ti-silicide formation, low and narrow distribution of sheet resistances both on n+/p+ poly-gate and source/drain diffusion layers are obtained. In addition, for DII process, the sheet resistances are lowered by 5 to 10% than those of PAI or Si ion-mixing only. Furthermore, the junction leakage current is reduced when the Si ion-mixing process is employed. Experimentally, based on the studied PAI and Si ion-mixing techniques, high-performance 0.2mm CMOS devices are fabricated successfully.
The characteristics of non-silicide polysilicon resistors in sub-quarter micron CMOS mixed-mode applications are reported in this thesis. Based on the presented sub-quarter micron CMOS borderless contact, both n+ and p+ polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate some important parameters of polysilicon resistors including electrical delta W (DW), interface resistance Rinterface, and bulk sheet resistance Rbulk. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS technology. In addition, the characteristics of voltage coefficient of resistor (VCR), temperature coefficient of resistor (TCR), and resistor mismatching (Rmis) are also studied.
In addition, a new and improved structure of polysilicon resistor for sub-quarter micron CMOS device applications is demonstrated and studied. A simple model is proposed to analyze its important parameters such as the voltage-dependent bulk sheet resistance, interface resistance, and VCR. An anomalous voltage-dependent characteristic of overall resistance is found mainly resulting from the existence of interface resistance. The proposed structure of polysilicon resistor with a larger effective width of interface region shows substantial suppression of the voltage-dependent resistance deviation caused by interface resistance. The reduction of VCR value is also obtained for the new structure. Consequently, from experimental results, the proposed structure can be used in precise (lower VCR) polysilicon resistors.
The effects of electrical and temperature stress on polysilicon resistors reliability in sub-quarter micron CMOS applications have been studied. The maximum current density (Jmax) is increased with the decrease of polysilicon resistor width W. The time-to-fail (TTF) value of the polysilicon resistor is decreased with increasing the electrical and temperature stress. A simple empirical formula is proposed in this study to predict the Jmax and lifetime of polysilicon resistors. Under a fixed dc current density (1.0×106A/cm2), the activation energies (Ea) for n+ and p+ polysilicon resistors at different temperature are 0.67 and 0.48 eV, respectively. In addition, at a fixed temperature of 473K, the current factors for n+ and p+ polysilicon resistors are 1.57x10-5 and 1.30x10-5 cm2/A, respectively, under different dc current densities. Therefore, these precise reliability performances offer the promise for ULSI design and fabrication.
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