A 24-bit Digital Audio Processor with a 50 MHz Phase-Locked Loop
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === In this thesis, a digital audio signal processor system with a 50 MHz phase-locked loop is designed. This system is a high performance 6-channel, which contains five full range (5) and one band-limited (.1) channels for 5.1-Channel audio. It is designed for au...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98791198392607954669 |