A Hybrid Method on Functional Testing for Embedded Processor Cores

• Main Authors: Min-Chien Chen, 陳旻謙
• Other Authors: Kuen-Jong Lee
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/81372199346131258023

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === With rapidly advanced VLSI manufacturing technology, it is possible to have an enormous number of transistors on a single die. These technology advances make system-on-chip (SOC) with shorter time-to-market, higher performance and lower manufacturing cost becoming an attractive solution in the IC design industry. SOCs usually have one or more general or special purpose processors. However, it is difficult to test these embedded processors because of the poor controllability and observability in SOC environment. Traditional scan-based testing for embedded processors will result in not only area overhead but also performance impact, and it is difficult to implement at-speed testing. Functional testing which uses only the instructions and data as test patterns is a good solution when area and performance are critical. In this thesis, a method which mixes manual and random test programs to functionally test the embedded processor is developed. To verify the practicability of the method, we use an ARM9 processor as the benchmark. Experimental results show the proposed method is a good solution for embedded processor test problems.