Clock Distribution Network for SoC

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc....

Full description

Bibliographic Details
Main Authors:	Cheng-Hsiung Tsai, 蔡正雄
Other Authors:	Yen-Tai Lai
Format:	Others
Language:	en_US
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/44764184048825295093

id	ndltd-TW-091NCKU5442070
record_format	oai_dc
spelling	ndltd-TW-091NCKU54420702016-06-22T04:14:02Z http://ndltd.ncl.edu.tw/handle/44764184048825295093 Clock Distribution Network for SoC 單晶片系統之時脈分佈網路 Cheng-Hsiung Tsai 蔡正雄碩士國立成功大學電機工程學系碩博士班 91 As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc. In this situation, the design methodology has to face a new challenge to resolve the issues of SoC. In this paper, we propose a new flexible clock distribution network design to solve the clock skew problem and support “plug-and-play” in SoC integrated overall SoC operation. Reduce the design cost due to iterative improvement in the integrated design. Yen-Tai Lai 賴源泰 2003 學位論文 ; thesis 48 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc. In this situation, the design methodology has to face a new challenge to resolve the issues of SoC. In this paper, we propose a new flexible clock distribution network design to solve the clock skew problem and support “plug-and-play” in SoC integrated overall SoC operation. Reduce the design cost due to iterative improvement in the integrated design.
author2	Yen-Tai Lai
author_facet	Yen-Tai Lai Cheng-Hsiung Tsai 蔡正雄
author	Cheng-Hsiung Tsai 蔡正雄
spellingShingle	Cheng-Hsiung Tsai 蔡正雄 Clock Distribution Network for SoC
author_sort	Cheng-Hsiung Tsai
title	Clock Distribution Network for SoC
title_short	Clock Distribution Network for SoC
title_full	Clock Distribution Network for SoC
title_fullStr	Clock Distribution Network for SoC
title_full_unstemmed	Clock Distribution Network for SoC
title_sort	clock distribution network for soc
publishDate	2003
url	http://ndltd.ncl.edu.tw/handle/44764184048825295093
work_keys_str_mv	AT chenghsiungtsai clockdistributionnetworkforsoc AT càizhèngxióng clockdistributionnetworkforsoc AT chenghsiungtsai dānjīngpiànxìtǒngzhīshímàifēnbùwǎnglù AT càizhèngxióng dānjīngpiànxìtǒngzhīshímàifēnbùwǎnglù
_version_	1718314110419992576

Clock Distribution Network for SoC

Similar Items