Clock Distribution Network for SoC
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc....
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44764184048825295093 |