Clock Distribution Network for SoC
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc....
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| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44764184048825295093 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc. In this situation, the design methodology has to face a new challenge to resolve the issues of SoC.
In this paper, we propose a new flexible clock distribution network design to solve the clock skew problem and support “plug-and-play” in SoC integrated overall SoC operation. Reduce the design cost due to iterative improvement in the integrated design.
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