Gate oxide reliability of advance CMOS device

• Main Authors: Shin-Duen Huang, 黃信惇
• Other Authors: Jone-Fang Chen
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/51931041390158072911

碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 91 === In this thesis, the sample is an 8inch wafer for 0.15μm technology n-MOSFET’s and p-MOSFET’s and we researched on oxide reliability. As devices scaling down, the device operational voltage and some characteristic still decreases slowly. The area and the thickness of the device oxide layer also decreased that varied the characteristic representation. So the dielectric oxide layer in MOSFET is to pay much attention to people. My experiment focuses on the difference between thin and thick oxide layer and finds the difference of the characteristic between before breakdown and after breakdown. First, I use ramp voltage test and constant voltage test to confer the difference of the I-V changes. Then I use the past breakdown definition to analyze the I-V curve. I want to find what influence on device between thin and thick oxide layer. Besides, I try to generalize it has the more accurate way to define the device breakdown. In these experiments, we used ICS (Interactive Characterization Software) to control HP4155B (Semiconductor Parameter Analyzer) produced by Agilent Technologies and 4200-SCS system produced by Keithley to finish various researches.