A Low-Voltage Embedded 4N SRAM
碩士 === 輔仁大學 === 電子工程學系 === 91 === This work describes a smart hidden refresh scheme for designing embedded 4N SRAM. An improved dynamic NOR decoder is also presented to achieve high-speed and low-power operation at low supply voltage. The smart refresh scheme can overcome the performance...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01708746894740564592 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 91 === This work describes a smart hidden refresh scheme for designing embedded 4N SRAM. An improved dynamic NOR decoder is also presented to achieve high-speed and low-power operation at low supply voltage. The smart refresh scheme can overcome the performance limitations of the conventional hidden refresh scheme. The refresh of a 4N cell is embedded in the period of a single cycle in normal read/write operation. The new design has the same I/O specification as that of 6T SRAM. It can be fabricated in standard CMOS processes as a small-area embedded memory. A test chip of 256×8 cells performs at 77MHz at a supply voltage of 1.2V. Since the area of the 4N cell is 40% less than 6T cell in the 0.25um 1P5M CMOS process, the area is 11% less than that of the 6T SRAM even with the area overhead associated with the smart hidden refresh. As the capacity or the number of SR-delay elements between two REF_MUXs increases, the reductive trend of chip area is less and less.
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