Research on the Design of Low Voltage Charge-Pump Phase Locked Loops for Clock Generator
碩士 === 中原大學 === 電子工程研究所 === 91 === The aim of this thesis is to design a low voltage charge pump phase locked loop ( CP-PLL ) for clock generator applications. The core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter, divide...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t8s27k |