A New Low-Power All-Digital Pulsewidth-Locked-Loop

A New Low-Power All-Digital Pulsewidth-Locked-Loop

碩士 === 國立中正大學 === 電機工程研究所 === 91 === A new low-power all-digital pulsewidth-locked-loop is presented in this thesis. For reducing the power consumption after locking, we split the pulse width detector into a pulse width detect circuit detecting the digital code of pulse width and a cycle time detect...

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Bibliographic Details
Main Authors:	You-Wei Yeh, 葉有偉
Other Authors:	Jinn-Shyan Wang
Format:	Others
Language:	zh-TW
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/20770251522888209227

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