A New Low-Power All-Digital Pulsewidth-Locked-Loop
碩士 === 國立中正大學 === 電機工程研究所 === 91 === A new low-power all-digital pulsewidth-locked-loop is presented in this thesis. For reducing the power consumption after locking, we split the pulse width detector into a pulse width detect circuit detecting the digital code of pulse width and a cycle time detect...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20770251522888209227 |