| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 91 === A new low-power all-digital pulsewidth-locked-loop is presented in this thesis. For reducing the power consumption after locking, we split the pulse width detector into a pulse width detect circuit detecting the digital code of pulse width and a cycle time detect circuit detecting the digital code of cycle time, besides add a frequency divided detection mechanism to the pulse width detect circuit which is the only active circuit after locking. Furthermore, for increasing the resolution and improving the poor resolution in high frequency operation, and reducing the complex of judgement circuit, we change the delay chain to an inverter chain with adaptive delay time.
The proposed ADPWLL has been fabricated in TSMC 0.25μm CMOS process, operating at 2.5V at 320MHz~450MHz. The power dissipation is about 9.7mW, pulse-width jitter is about 7ps after locking. The locking time of duty-cycle is less than 37 clock cycles. Furthermore, we integrated an all-digital delay-locked loop into this integrated circuit, and it performs duty-cycle and phase locking within 47 clock cycles. The integrated circuit has been implemented the layout design. Its core area is about 0.2538mm2.
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