Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths

碩士 === 國立中正大學 === 資訊工程研究所 === 91 === This Thesis proposes an efficient hardware design for the one-dimensional (1-D) discrete Fourier transform (DFT) and its inverse with variable lengths. By combining radix-2/4/8 algorithm, cyclic convolution formulation, sub-expression sharing and Cooly-Tuckey dec...

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Bibliographic Details
Main Authors:	Chih-Ta Chien, 簡志達
Other Authors:	Jiun-In Guo
Format:	Others
Language:	zh-TW
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/09878445894553887482

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spelling	ndltd-TW-091CCU003921202016-06-24T04:15:54Z http://ndltd.ncl.edu.tw/handle/09878445894553887482 Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths 以加法器為基礎之高效能可變長度一維正反向離散傅利葉轉換數位矽智財設計與實作 Chih-Ta Chien 簡志達碩士國立中正大學資訊工程研究所 91 This Thesis proposes an efficient hardware design for the one-dimensional (1-D) discrete Fourier transform (DFT) and its inverse with variable lengths. By combining radix-2/4/8 algorithm, cyclic convolution formulation, sub-expression sharing and Cooly-Tuckey decomposition algorithm together, we have developed a parameterized hardware design for the DFT/IDFT of variable lengths ranging from 64 to 4096 points. Furthermore, we have also implemented a parameterized DSP Intellectual Property (IP) core with proposed design for meeting the system requirements of different system-on-chip (SOC) applications. Jiun-In Guo 郭峻因 2003 學位論文 ; thesis 0 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立中正大學 === 資訊工程研究所 === 91 === This Thesis proposes an efficient hardware design for the one-dimensional (1-D) discrete Fourier transform (DFT) and its inverse with variable lengths. By combining radix-2/4/8 algorithm, cyclic convolution formulation, sub-expression sharing and Cooly-Tuckey decomposition algorithm together, we have developed a parameterized hardware design for the DFT/IDFT of variable lengths ranging from 64 to 4096 points. Furthermore, we have also implemented a parameterized DSP Intellectual Property (IP) core with proposed design for meeting the system requirements of different system-on-chip (SOC) applications.
author2	Jiun-In Guo
author_facet	Jiun-In Guo Chih-Ta Chien 簡志達
author	Chih-Ta Chien 簡志達
spellingShingle	Chih-Ta Chien 簡志達 Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
author_sort	Chih-Ta Chien
title	Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
title_short	Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
title_full	Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
title_fullStr	Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
title_full_unstemmed	Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
title_sort	design and implementation of the high-performance adder-based ip core for the 1-d dft/idft with variable lengths
publishDate	2003
url	http://ndltd.ncl.edu.tw/handle/09878445894553887482
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Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths

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