Design and Implementation of the High-performance Adder-based IP Core for the 1-D DFT/IDFT with Variable Lengths
碩士 === 國立中正大學 === 資訊工程研究所 === 91 === This Thesis proposes an efficient hardware design for the one-dimensional (1-D) discrete Fourier transform (DFT) and its inverse with variable lengths. By combining radix-2/4/8 algorithm, cyclic convolution formulation, sub-expression sharing and Cooly-Tuckey dec...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09878445894553887482 |