Block Based Fetch Engine for SuperScalar Processor

• Main Authors: Zheng Kuo Wu, 吳正國
• Other Authors: Jong Jiann Shieh
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/12237410348440847040

碩士 === 大同大學 === 資訊工程研究所 === 90 === The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one branch prediction per cycle and therefore, can fetch no more than one basic block per cycle. While fetching a single basic block each cycle is sufficient for implementations that issue at most four instructions per cycle, it is not for processors with higher peak issue rates. If multiple block prediction is used, the fetch unit can at least fetch multiple contiguous basic blocks. In this paper we proposed architecture which combine the extended branch target buffer with the block cache to fetch multiple blocks, the extended branch target buffer to store multiple branch target. Block cache keeps the instruction sequence that is collected at commit stage as blocks. These blocks are renamed and stored in the extended branch target buffer as the basic fetching unit The proposed architecture has been simulated using simpleScale 2.0 simulator. The results show that the average instruction fetch per cycle reach 4.4 instructions, the average instruction issued per cycle is 3.2 instructions and the average IPC is 2.07. As compare to the base machine, we got 2.6 to 4.55, 1.9 to 3.2 and 1.2 to 2.07 respectively.