Showing 1 - 20 results of 45 for search 'Jong Jiann Shieh', query time: 0.09s Refine Results
  1. 1
    A Study of Improving Fetch and Execute Engine for Simultaneous Multithreading Processors
    by Shih-hung Yang, 楊適鴻
    Published 2007
    Other Authors: “...Jong-Jiann Shieh...”
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  2. 2
    A Study of Instruction Prefetch Mechanism on Simultaneous Multithreading Architecture
    by Chih-Ming Tsao, 曹志銘
    Published 2006
    Other Authors: “...Jong-Jiann Shieh...”
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  3. 3
    Combine the Value Prediction and Data Reuse in RISC Architecture
    by Ji-Ching Chang, 張季青
    Published 1999
    Other Authors: “...Jong-Jiann Shieh...”
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  4. 4
    Study on Instruction Reuse in RISC Architecture
    by Yichen Liu, 劉亦峻
    Published 1999
    Other Authors: “...Jong-Jiann Shieh...”
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  5. 5
    A Multiple Blocks Fetch Engine for High Performance Superscalar Processor
    by Yung-Chung Wu, 吳永崇
    Published 2001
    Other Authors: “...Jong-Jiann Shieh...”
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  6. 6
    Design and Implementation of the Enhanced Block-based Trace Cache Mechanism
    by Shu-Chang Liang, 梁書彰
    Published 2001
    Other Authors: “...Jong-Jiann Shieh...”
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  7. 7
    Implementation of Combing the Implementation of Combing the Data Reuse
    by Der Shan Tzeng, 曾德山
    Published 2001
    Other Authors: “...Jong-Jiann Shieh...”
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  8. 8
    Exploiting Speculative Value Reuse Using Value Prediction
    by Chia-Hung Liao, 廖家宏
    Published 2001
    Other Authors: “...Jong-Jiann Shieh...”
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  9. 9
    Technique of Reducing the Impact in Control and Data Speculation
    by Tzu-Chieh Day, 戴子捷
    Published 2005
    Other Authors: “...Jong-Jiann Shieh...”
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  10. 10
    An Issue Logic for Superscalar Microprocessors
    by Feng-Jiann Shiao, 蕭丰健
    Published 2003
    Other Authors: “...Jong-Jiann Shieh...”
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  11. 11
    Power-aware shortcut tree routing algorithm
    by Wei-hsiang Peng, 彭韋翔
    Published 2012
    Other Authors: “...Jong-Jiann Shieh...”
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  12. 12
    Design and Implementation of MMU and TLB for Advanced x86 Compatible Microprocessors
    by Hsu- Ming Kai, 許明愷
    Published 1998
    Other Authors: “...Jong-Jiann Shieh...”
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  13. 13
    THE DESIGN AND IMPLEMENTATION OF A X86 COMPATIBLE INSTRUCTION CACHE
    by Lu- Jaming, 呂家銘
    Published 1998
    Other Authors: “...Jong-Jiann Shieh...”
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  14. 14
    Use Hybrid Echo Instruction to Reduce Code-size In MIPS
    by Ya-Chen Hsieh, 謝雅真
    Published 2013
    Other Authors: “...Jong-Jiann Shieh...”
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  15. 15
    Study on ZigBee Indoor Position
    by Chiu-Wen Chen, 陳秋汶
    Published 2012
    Other Authors: “...Jong-Jiann Shieh...”
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  16. 16
    Sorting Unit For FPGA-based System
    by Wei-Ting Chung, 鍾瑋庭
    Published 2012
    Other Authors: “...Jong-Jiann Shieh...”
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  17. 17
    The Design of an E-book Reader Assistive Devices
    by Wen-wen Ma, 馬汶汶
    Published 2011
    Other Authors: “...Jong-Jiann Shieh...”
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  18. 18
    Empirical Performance Evaluation of a Pipelined Multibus System
    by Shao-Rong Lu, 盧紹榮
    Published 1994
    Other Authors: “...Jong-Jiann Shieh...”
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  19. 19
    Process Partitioning and Scheduling on Shared Memory Systems
    by Tsai-Yih Kuo, 郭蔡義
    Published 1994
    Other Authors: “...Jong-Jiann Shieh...”
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  20. 20
    An Algorithm for PLA Simple Column Folding
    by Dong-Yie Chen, 陳東役
    Published 1993
    Other Authors: “...Jong-Jiann Shieh...”
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