Design and Analysis of a Novel All Digital Phase-Locked Loop

• Main Authors: Ta-Wei Liu, 劉大維
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/51110173758933390178

碩士 === 淡江大學 === 電機工程學系 === 90 === Recently, phase-locked loop (PLL) has been widely used in the field of computers and communications systems applications such as frequency synthesizer, data recovery circuit, and delay de-skewing. In the tradition PLL scheme, a low-pass filter (LPF) consisting of resistors and capacitors is utilized to get rid of the high frequency signal generated by its charge-pump circuit. However, resistors and capacitors in the integrated circuits have great variation in their physical values. Hence, we proposed a novel architecture of All Digital Phase-Lock Loop to solve the problems in traditional PLL. The fundamental concept of our ADPLL is based on ADPLL proposed by Motorola in 1995. In our ADPLL, the new binary search algorithm has “revisit” and “relock” ability. The Phase Frequency Detector (PFD) is a special type for the novel ADPLL such that it just needs one PFD to complete all of locking process. The ADPLL is designed and implement by TSMC’s 0.35um 1P4M CMOS process for 3.3V applications. The frequency locking range of the proposed ADPLL is about 282MHz to 675MHz.