Automatic Verilog Code Generation of an 8-Bit RISC Micro-controller

• Main Authors: Jui-Min Lai, 賴瑞明
• Other Authors: Yun-Tai Husueh
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/55957143643896340979

碩士 === 南台科技大學 === 電子工程系 === 90 === In this paper, we describe a design method, which can automatically generate verilog code for an 8-bit RISC micro-controller with a user-definable instruction set. With this method, one can shorten the verilog coding time, increase the efficiency of verilog coding, and decrease the man-hour requirement. It is easy to design an 8-bit RISC micro-controller using this method. First of all, the architecture that satisfies the design specification has to be fixed. Then, according to the architecture, the I/O ports, memory size, address space, etc., should be defined and assigned. The most important step is to define the instruction set. The detail information defined in the instruction set, such as operation, operands, flags, and the like, will be used substantially later during automatic verilog code generation. The automatic verilog code generate program is written in C/C++ language. This program can generate all the required modules of the 8-bit RISC micro-controller. We use this program to generate a PIC16C6X verilog code for testing. During the debugging stage, some fine tune of the automatically generated verilog code is still required.