Design of A PLL with Fast-Lock and Low Jitter
碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === In this thesis, a methodology is applied to design a fast lock phase lock loop and programmable phase bandwidth. The complete design flow is presented from the system level specification to layout and measurement result. This high level system is described using...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10837112042140208613 |