| Summary: | 博士 === 國立臺灣大學 === 電機工程學研究所 === 90 === A novel repeated spike oxidation (RSO) technique was employed in RTP system. Simulation results predict both the temperature distributions on wafer and in chamber would be improved by this RSO method. It is suggested that the improvement in wafer temperature uniformity is mainly caused by self-compensation in radiation heat absorption rate. Experimental data pointed out that the new method can produce more uniform oxide thickness under an intentionally created nonuniform heating environment. Under a normal heating system, the effect of 100℃ spike amplitude RSO is not observed in ellipsometry data but appears in the distribution of leakage current magnitude on the whole wafer. By enlarging the spike amplitude to 200℃ , oxide prepared by RSO exhibit better uniformity than conventional method, which could be read from the ellipsometry data.
Next, the investigation of the difference in electrical properties between RSO and Typical samples was performed. First RSO samples were oxidized by ramping the temperature from 750 to 850℃ and Typical samples were oxidized by keeping the temperature at 850℃. Under this conditions RSO and Typical samples have no difference in electrical properties including tunneling current under gate injection, flatband voltage, interface state density, and FTIR spectrum, and RSO sample has a disadvantage that more silicon bulk traps were produced and results in a higher substrate injection current. Then, RSO samples were oxidized by ramping the temperature from 600 to 800℃ and Typical samples were oxidized by keeping the temperature at 700℃. Under this temperature sentiment, thin gate oxide with low leakage could be prepared by RSO technique in the comparison under similar quantum mechanical fitted effective oxide thickness. With respect to the conventional one, this new technique had relatively lower average process temperature. The reduction of tunneling current in RSO sample was not due to the flat band voltage shift or electron trapping during measurement. Experimental results indicated that it was possibly due to the reduction of interface states density. The improvement in oxide thickness uniformity might be another reason. Also, RSO samples appear more silicon bulk traps than Typical ones. Moreover, RSO and Typical samples in the same optical thickness exhibit different electrical effective thickness, the actual reason is still unknown. High temperature 850℃ anneal was performed on the low temperature grown RSO and Typical samples in section3-4. After POA, RSO+A and Typical+A samples exhibit the same performance on tunneling current, flatband voltage, interface state densities, and electrical effective oxide thickness. Also, the additional silicon bulk traps in RSO samples are removed after POA.
Then, a novel repeated spike treatment (RST), was employed to bake the silicon wafer in N2 ambient before oxidation. These obtained RST+O samples, in comparison with the Typical+O samples, which were baked with a conventional temperature profile before the same oxidation process, had three apparent local thick oxide regions that adjoined to the contacts of the three-pin quartz holder. It was observed that defects could be created on silicon surface due to the high thermal stress at contacts during RST and the oxidation rate of these damaged zones were enhanced. The induced defects could be clearly observed by naked eyes and microscopes. The leakage current and interface state density of the RST+O samples were higher and the uniformity was worse than those of the Typical+O samples. These enhanced degradation phenomenon could be caused by the RST, which resulted in rough Si/SiO2 interface and nonuniform oxide thickness.
Moreover, mechanical stress effects on MOS devices were studied. Wafer cutting effects on MOS devices’ performance was first demonstrated. The cutting of wafer results in breaking of atomic bonding both at Si/SiO2 interface and silicon bulk. These make increases in substrate injection current of MOS device especially which located near the cutting path. There is another mechanism that may affect the devices characteristic after wafer cut. The distribution of inherent tensile stress sustained by silicon substrate was suggested to be dependent on chip shape that changes after wafer cut. The change of stress magnitude influence the amount of bandgap narrowing effect and thus the leakage current. Devices performance differs before and after wafer cuttings. The effect of external stress on MOS structure with ultrathin gate oxide (~1.5nm) was then studied. J-V characteristics of fresh and stressed samples revealed that the tensile stress had little effect on J-V curves, whereas the compressive stress obviously increased the leakage current by about several hundred in percentages with respect to the fresh sample, in both positive and negative gate biases. This increase in leakage current was suggested to be attributed to the increase of interface states and silicon bulk traps under external compressive stress in MOS device with an inherent tensile stressed silicon. Both devices located at chip center and edge exhibit the similar behavior. In addition, we also found that once the device was damaged by the previously applied compressive stress, the second applied compressive stress of the same magnitude would not create more damage unless the device was breakdown.
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