Clock Tree Buffer Sizing with Applying Connective Skew
碩士 === 國立清華大學 === 資訊工程學系 === 90 === Clock designs play an important role in modern VLSI designs. Among clock network designs, the buffered clock tree architecture is the most popular clock network design adopted in modern VLSI designs. In this thesis, we have proposed a new skew concept,...
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37535306826454204141 |