Equivalent Circuit Extraction of Embedded High-speed Interconnects by Combining FDTD method and Layer Peeling Technique
碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === We proposes an efficient algorithm for extracting SPICE-compatible circuits of embedded interconnect structures from FDTD-simulated time-domain reflections. A layer-peeling technique (LPT) is used to obtain the time-domain step response of the interconnects...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29438662626398788105 |