The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit
碩士 === 國立交通大學 === 電機與控制工程系 === 90 === The present dissertation studies the system architecture and sensing circuits of a capacitive micro-accelerometer. Sigma-delta concept is used as the system architecture of micro-accelerometer for the purpose of high S/N ratio, digital output and clos...
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ndltd-TW-090NCTU05910822015-10-13T10:08:07Z http://ndltd.ncl.edu.tw/handle/14106462106668279365 The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit 電容式微加速度計系統及感測電路之設計、分析與模擬 Jiun-Cheng Chen 陳俊成 碩士 國立交通大學 電機與控制工程系 90 The present dissertation studies the system architecture and sensing circuits of a capacitive micro-accelerometer. Sigma-delta concept is used as the system architecture of micro-accelerometer for the purpose of high S/N ratio, digital output and closed-loop electrostatic feedback. Furthermore, by reducing damping coefficient or increasing spring coefficient and proof mass, we are able to produce high quality factor. By using vacuum packaging, we can further reduce Brownian noise. Note that when reducing the effects of these noises, the remaining noises compared to circuit noise can be neglected. Two common used circuits are analyzed in the sensing circuit with the presence of the non-ideal characteristics of the circuits. By performing a series of analysis, we have used a modified version of corrected double sampling to reduce non-ideal circuit characteristic except thermal noise. In order to increase sensing resolution, we performed the optimization to the Op amp thermal noise. Finally, we are able to develop a capacitive micro-accelerometer system model for the purpose of simulating the dynamic behavior. Note that with the model, we are able to compare different systems by tuning its corresponding parameters. Here, we verified that the analysis result is closed to the theory. For the switch capacitor circuit, due to the switch error effect, the result has experienced a 5% difference than theory. An operational amplifier with a 57M Hz unit-gain bandwidth, and a 204K Hz frequency of oscillator and a clock generator were designed and verified. The object of this dissertation is to design a ±5g input which has a ±5v output voltage. The simulation result show that at 100K Hz sampling frequency, the system possesses correct output signal when input signal is in the range of ±4.7g, and the output signal has a 0.1v maximum error. Jin-Chern Chiou Yon-Ping Chen 邱俊誠 陳永平 2002 學位論文 ; thesis 66 zh-TW |
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碩士 === 國立交通大學 === 電機與控制工程系 === 90 === The present dissertation studies the system architecture and sensing circuits of a capacitive micro-accelerometer. Sigma-delta concept is used as the system architecture of micro-accelerometer for the purpose of high S/N ratio, digital output and closed-loop electrostatic feedback. Furthermore, by reducing damping coefficient or increasing spring coefficient and proof mass, we are able to produce high quality factor. By using vacuum packaging, we can further reduce Brownian noise. Note that when reducing the effects of these noises, the remaining noises compared to circuit noise can be neglected. Two common used circuits are analyzed in the sensing circuit with the presence of the non-ideal characteristics of the circuits. By performing a series of analysis, we have used a modified version of corrected double sampling to reduce non-ideal circuit characteristic except thermal noise. In order to increase sensing resolution, we performed the optimization to the Op amp thermal noise. Finally, we are able to develop a capacitive micro-accelerometer system model for the purpose of simulating the dynamic behavior. Note that with the model, we are able to compare different systems by tuning its corresponding parameters. Here, we verified that the analysis result is closed to the theory. For the switch capacitor circuit, due to the switch error effect, the result has experienced a 5% difference than theory. An operational amplifier with a 57M Hz unit-gain bandwidth, and a 204K Hz frequency of oscillator and a clock generator were designed and verified. The object of this dissertation is to design a ±5g input which has a ±5v output voltage. The simulation result show that at 100K Hz sampling frequency, the system possesses correct output signal when input signal is in the range of ±4.7g, and the output signal has a 0.1v maximum error.
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author2 |
Jin-Chern Chiou |
author_facet |
Jin-Chern Chiou Jiun-Cheng Chen 陳俊成 |
author |
Jiun-Cheng Chen 陳俊成 |
spellingShingle |
Jiun-Cheng Chen 陳俊成 The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
author_sort |
Jiun-Cheng Chen |
title |
The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
title_short |
The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
title_full |
The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
title_fullStr |
The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
title_full_unstemmed |
The Design, Analysis and Simulation of Capacitive Micro-Accelerometer System and Sensing Circuit |
title_sort |
design, analysis and simulation of capacitive micro-accelerometer system and sensing circuit |
publishDate |
2002 |
url |
http://ndltd.ncl.edu.tw/handle/14106462106668279365 |
work_keys_str_mv |
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