New Structure Development and Key Process Technologies for Low Temperature Processed Poly-Si Thin-Film Transistors

• Main Authors: Darren Chi-Hsiang Chen, 陳奇祥
• Other Authors: Ching-Fa Yeh
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/24332302147599667815

博士 === 國立交通大學 === 電子工程系 === 90 === Utilizing polycrystalline silicon thin-film transistors (poly-Si TFT’s) as on-glass pixel switching elements and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCDs). Low-temperature processes (LTP) for poly-Si TFT’s are important issues. In this thesis, we utilized several low-temperature technologies to improve poly-Si TFT’s' performance, including new structure development, gate-oxide post-annealing, channel defect passivation and metal induced recrystallization of α-Si. First of all, ON/OFF current ratio of Poly-Si TFT’s has been improved by using a novel structure called the dual-buffer drain (DBD). The new DBD TFT not only reduces the anomalous off-current, but also maintains a high on-current. It mainly combines features of the double-gate and the field-induced drain structures, so that owns advantages of low electric field near the drain junction and good drain junction characteristics. Furthermore, it will be shown that the DBD TFT is superior in off-current stability to the FID TFT. Finally, we will discuss high voltage operation for the DBD TFT. The technology of growing liquid-phase deposited (LPD) silicon dioxide has been successfully used in fields of gate insulator and insulating capping layer. Here, a novel idea of charged LPD oxide by hydrogen plasma treatment is also proposed and applied in a new TFT structure as its interlayer. The new structure is named as self-induced lightly-doped-drain (SI-LDD) poly-Si TFT’s. The new structure, utilizing charged LPD interlayer, not only effectively reduces OFF-current but also still feeds enough large ON-current. In the reliability, The SI-LDD poly-Si TFT’s reveals an acceptable instability under large bias stress. On the other hand, low temperature (~300oC) N2O-plasma post-treatment for liquid-phase deposited (LPD) gate oxide has been proposed for the first time. It successfully takes the place of conventional furnace annealing in O2 ambient. Results of physicochemical and electrical characteristics show that N2O-plasma post-treated LPD-SiO2 has high electrical breakdown field and low interface state density. In addition, N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with the short time re-oxidation in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low temperature processed (LTP) poly-Si TFT’s. The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result, as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFT’s. Futhermore, for defect passivation technology of LTP poly-Si TFT’s, we utilize deuterium (D2) plasma to replace the conventional hydrogen (H2) plasma treatment. D2-plasma passivation can improve enormously the TFT’s' performance, particularly in carrier mobility and reliability. This improvement can be attributed to the giant isotope effect and strong coupling efficiencies by the Si-D bonds. In addition, the effects of D2-plasma followed by N2O-plasma passivation (D2-N2O-plasma) on LTP poly-Si TFT’s were also investigated. It was found that D2-N2O-plasma passivation is more effective in improving the hot-carrier immunity of poly-Si TFT’s than D2-plasma or N2O-plasma passivation only. Finally, Low-temperature (<550oC) Ni-metal induced lateral crystallization (MILC) has been applied to high performance poly-Si TFT’s process. The MILC-TFT with Si2H6 deposited-Si layer performs better performance than that with SiH4 deposited -Si layer due to its easier re-crystallized properties. Moreover, a smart “U-shape” double-gate structure for MILC-TFT’s is proposed to improve the problem of metal-silicide residues and reduce OFF-current. The OFF-current is reduced significantly two orders of magnitude and the threshold voltage is improved 35%. For hot-carrier reliability, MILC-TFT’s show much smaller degradation than SPC-TFT’s. The deuterated MILC-TFT’s also have better reliability than the hydrogenated MILC-TFT’s. Finally, a degradation model of donor-like trap states near the drain region is qualitatively proposed to explain the surprising improvement in OFF-state characteristics for MILC-TFT’s after hot-carrier stress.