| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 90 === Recently, the gated-diode (GD) drain current measurement has been widely used to characterize hot-carrier degradation in MOSFET’s. The generation/recombination current in the drain-to-well diode as a function of the gate voltage, combined with two-dimensional numerical simulation, provides a sensitive tool for detecting the spatial distribution and density of interface defects. In addition, the DCIV measurement is also one of the most popular methods dealing with the hot carrier induced degradations in MOSFET’s. It uses gate terminal voltage, VG, to modulate the surface potential, from which, the parasitic BJT can measure different recombination currents from base terminal. In this study, for the first time, we have compared the difference between the DCIV and the gated-diode measurements. We found that these two methods monitored the same incremental recombination current induced by the oxide damage. The only difference is their forward diffusion current value.
As device channel length is continuously scaled down, the gate oxide thickness is also scaled down to maintain good short channel effect and driving current. When the gate oxide thickness is scaled down below 30Å, direct tunneling current occurs. In the DCIV method, the recombination current from the base terminal will be overwhelmed by the direct tunneling current from the base terminal to the gate terminal. On the other hand, the drain current will be affected by the drain edge tunneling current in gated-diode measurements. In this study, we combine the advantages of both GD and DCIV methods to propose a new measurement method. The new method uses the strategy of forward bias in DCIV and a gated-diode configuration. This new measurement approach is superior to the typical DCIV method. Besides, in the experimental setup of this new method, the electrical field of the overlap region will be smaller and the recombination current will be easier to detect than the gate tunneling current by increasing the forward pn junction bias. It was shown that the new measurement is able to evaluate the oxide damage in pMOSFET’s with gate oxide thickness as thin as 12Å.
We have applied the new GD measurement to study the hot carrier degradation in nMOSFET’s and pMOSFET’s. For substrate hot carrier stress, we can directly observe from the gated-diode current shape that most of the degradation occurs in the whole channel region. For channel hot carrier stress, we can also directly find from the gated-diode line shape that the worst degradation occurs near the drain side region. For both nMOSFET’s and pMOSFET’s under hot carrier stress, the most serious damage happens at Vg = Vd stress condition. In NBTI experiments for stressing pMOSFET at Vg = Vd and high temperature, we also found that large interface states were generated near the channel edge region. Both hot carrier and NBTI effect result in the channel edge damage.
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