Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology

博士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === In this thesis two dielectric materials, silicon dioxide SiO2 and tantalum pentoxide Ta2O5, were investigated. In the development of the integrated circuit, the MOS device plays a very important role. The silicon dioxide SiO2 is used to act as its insulator la...

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Main Authors: Jiann-Shing Lee, 李建興
Other Authors: Shi-Chung Sun
Format: Others
Language:en_US
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/xe679m
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description 博士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === In this thesis two dielectric materials, silicon dioxide SiO2 and tantalum pentoxide Ta2O5, were investigated. In the development of the integrated circuit, the MOS device plays a very important role. The silicon dioxide SiO2 is used to act as its insulator layer. When the device dimension is scaled down, the thickness of the insulator layer is also reduced. Owing to the scaling of the oxide thickness, the increase of the oxide leakage current is inevitable. For minimizing the gate leakage current, many new technologies are recommended to grow high quality thin oxide film. The rapid thermal processing (RTP) system using in-situ steam generation (ISSG) was employed to grown thin gate oxides in this thesis. Experimental results indicate that oxides grown by diluted steam rapid thermal oxidation exhibit significant reduction in gate leakage current, increase in breakdown field, and device reliability, as compared to conventional furnace-grown wet oxides. Furthermore, ISSG oxides showed better electric characteristics than dry RTO oxides. And the post-annealing effects of ISSG oxide in N2 and nitric oxide (NO) ambient were also examined. It was found that the sample with post-annealing in NO ambient shows less charge trapping, higher charge-to-breakdown, higher electron mobility and smaller device degradation under channel hot carrier stress. This is attributed to the improvement of structural transition layer by the incorporation of nitrogen near and at Si/SiO2 interface during NO annealing. In addition to the quality improvement of the silicon dioxide, the high dielectric constant material has also been considered to substitute for the silicon dioxide to act as the gate dielectric. In this thesis tantalum pentoxide Ta2O5 was researched due to its high dielectric constant of about 25, good step coverage, and good dielectric strength. Tantalum pentoxide (Ta2O5) thin film with an initial thickness of 10.5 nm was deposited onto p-type silicon substrate by low-pressure chemical vapor deposition (LPCVD), and subsequently annealed in O2 ambient at 500 oC to 800 oC for 30 minutes for improving its electrical characteristics. It was found that the leakage current of the Ta2O5/SiOx capacitor was controlled by the Ta2O5 layer when the annealing temperature was lower than 700 oC. On the other hand, the leakage current was controlled by the interfacial oxide layer (SiOx) when the annealing temperature was higher than 700 oC. Furthermore, higher annealing temperatures will result in a rougher sample surface and a higher leakage current due to Ta2O5 crystallization. For the as-deposited Ta2O5 films, in low electric field region, the leakage current could be dominated either the hopping conduction or Poole-Frenkel emission. Or both of the two conduction mechanisms exist in the leakage current conduction. In high electric field Fowler-Nordheim tunneling was the main leakage mechanism. After the crystallization of the Ta2O5 film, the conduction mechanism in high electric field was dominated by the Poole Frenkel emission. But at low electric field the conduction mechanism was not obvious. It could be affected by the formation of the grain boundary in the Ta2O5 film. And highly reliable ultrathin low-pressure chemical vapor deposited (LPCVD) tantalum pentoxide (Ta2O5) capacitors were fabricated by using high-density plasma (HDP) annealing in N2O at 400 oC after the film deposition. The low temperature plasma annealing was used for minimizing the thermal budget. It was found that HDP annealing in N2O could significantly reduce the leakage current of Ta2O5 capacitors so as to produce better time-dependent dielectric breakdown characteristics than either conventional oxygen-plasma annealing or HDP annealing in O2. It was also found that HDP annealing in N2O would not significantly increase the thickness of interfacial SiOx layer between Ta2O5 and the underlying silicon substrate. The leakage current mechanism was also investigated. For the HDP N2O annealed Ta2O5 films, it was found that the main leakage mechanism was Schottky emission in low electric field and Poole-Frenkel emission in high electric field.
author2 Shi-Chung Sun
author_facet Shi-Chung Sun
Jiann-Shing Lee
李建興
author Jiann-Shing Lee
李建興
spellingShingle Jiann-Shing Lee
李建興
Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
author_sort Jiann-Shing Lee
title Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
title_short Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
title_full Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
title_fullStr Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
title_full_unstemmed Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology
title_sort study of ultrathin gate dielectric and high k gate dielectric for cmos technology
publishDate 2002
url http://ndltd.ncl.edu.tw/handle/xe679m
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spelling ndltd-TW-090NCKU54421792018-06-25T06:05:29Z http://ndltd.ncl.edu.tw/handle/xe679m Study of Ultrathin Gate Dielectric and High K Gate Dielectric for CMOS Technology 超薄閘極介電層與高介電閘極介電層於CMOS製程技術之研究 Jiann-Shing Lee 李建興 博士 國立成功大學 電機工程學系碩博士班 90 In this thesis two dielectric materials, silicon dioxide SiO2 and tantalum pentoxide Ta2O5, were investigated. In the development of the integrated circuit, the MOS device plays a very important role. The silicon dioxide SiO2 is used to act as its insulator layer. When the device dimension is scaled down, the thickness of the insulator layer is also reduced. Owing to the scaling of the oxide thickness, the increase of the oxide leakage current is inevitable. For minimizing the gate leakage current, many new technologies are recommended to grow high quality thin oxide film. The rapid thermal processing (RTP) system using in-situ steam generation (ISSG) was employed to grown thin gate oxides in this thesis. Experimental results indicate that oxides grown by diluted steam rapid thermal oxidation exhibit significant reduction in gate leakage current, increase in breakdown field, and device reliability, as compared to conventional furnace-grown wet oxides. Furthermore, ISSG oxides showed better electric characteristics than dry RTO oxides. And the post-annealing effects of ISSG oxide in N2 and nitric oxide (NO) ambient were also examined. It was found that the sample with post-annealing in NO ambient shows less charge trapping, higher charge-to-breakdown, higher electron mobility and smaller device degradation under channel hot carrier stress. This is attributed to the improvement of structural transition layer by the incorporation of nitrogen near and at Si/SiO2 interface during NO annealing. In addition to the quality improvement of the silicon dioxide, the high dielectric constant material has also been considered to substitute for the silicon dioxide to act as the gate dielectric. In this thesis tantalum pentoxide Ta2O5 was researched due to its high dielectric constant of about 25, good step coverage, and good dielectric strength. Tantalum pentoxide (Ta2O5) thin film with an initial thickness of 10.5 nm was deposited onto p-type silicon substrate by low-pressure chemical vapor deposition (LPCVD), and subsequently annealed in O2 ambient at 500 oC to 800 oC for 30 minutes for improving its electrical characteristics. It was found that the leakage current of the Ta2O5/SiOx capacitor was controlled by the Ta2O5 layer when the annealing temperature was lower than 700 oC. On the other hand, the leakage current was controlled by the interfacial oxide layer (SiOx) when the annealing temperature was higher than 700 oC. Furthermore, higher annealing temperatures will result in a rougher sample surface and a higher leakage current due to Ta2O5 crystallization. For the as-deposited Ta2O5 films, in low electric field region, the leakage current could be dominated either the hopping conduction or Poole-Frenkel emission. Or both of the two conduction mechanisms exist in the leakage current conduction. In high electric field Fowler-Nordheim tunneling was the main leakage mechanism. After the crystallization of the Ta2O5 film, the conduction mechanism in high electric field was dominated by the Poole Frenkel emission. But at low electric field the conduction mechanism was not obvious. It could be affected by the formation of the grain boundary in the Ta2O5 film. And highly reliable ultrathin low-pressure chemical vapor deposited (LPCVD) tantalum pentoxide (Ta2O5) capacitors were fabricated by using high-density plasma (HDP) annealing in N2O at 400 oC after the film deposition. The low temperature plasma annealing was used for minimizing the thermal budget. It was found that HDP annealing in N2O could significantly reduce the leakage current of Ta2O5 capacitors so as to produce better time-dependent dielectric breakdown characteristics than either conventional oxygen-plasma annealing or HDP annealing in O2. It was also found that HDP annealing in N2O would not significantly increase the thickness of interfacial SiOx layer between Ta2O5 and the underlying silicon substrate. The leakage current mechanism was also investigated. For the HDP N2O annealed Ta2O5 films, it was found that the main leakage mechanism was Schottky emission in low electric field and Poole-Frenkel emission in high electric field. Shi-Chung Sun Shoou-Jinn Chang 孫喜眾 張守進 2002 學位論文 ; thesis 116 en_US