The Design and Realization of Analog Direct-Skew-Detector Synchronous Mirror Delay Circuit
碩士 === 華梵大學 === 機電工程研究所 === 90 === This thesis presents a fast clock deskewing method with an analog direct-skew-detect synchronous mirror delay (ASMD). The clock skew is affected by various independent factors, such as the fabrication process, the power-supply voltage, the temperature, a...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39544821972151720098 |