Study of Lateral Power MOSFETs on SOI

• Main Authors: Wei-Ting Kuo, 郭威廷
• Other Authors: Jyh-Ling Lin
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/95137612367402628390

碩士 === 華梵大學 === 機電工程研究所 === 90 === In the high speed、high frequency times, this paper will study in development of power devices which have lower leakage current and parasitic capacitance effect by using Silicon-On-Insulator (SOI) technology, lower power consumption and fast switching rate is obtained in widely application area. In the conventional LDMOSFETs structure, the drift region usually requires a thicker and lower doped epitaxial layer for higher breakdown voltage. However, the important point to note is the blocking capability and turn-on resistance is very sensitive to doping concentration. Breakdown voltage versus on-state resistance trade-off has always been a prime concern in the design of power devices. In this condition, this trade-off of power devices will limit the application area. In this paper, we will overcome this limitation by RESURF technology and enhance blocking capability efficiently on thinner epitaxtial layer for substantial superior performance. On the other hand, new device concepts called Super-Junction (SJ) and Unbalance Super-Junction (USJ) will be used. The drift region of device is replaced by alternatively stacked, difference width heavily doped N and P strip. These concepts will provide lower on-state resistance, uniform electric field and optimum blocking capability in the same times. In this paper, we will focus in the static characteristic of device. Finally, we will intend to present simulated and experiential results of superior performance LDMOSFETs based on newly concept. The performance comparison of the conventional LDMOSFETs, Super-Junction and Unbalance Super-Junction will be also given. In this paper, the series parameters of experiment will analyze by simulator TMA including TSUPRE-4, 2D-MEDICI and 3D-DAVINCI for understanding characteristics of Power devices. The simulated results will accord to the spec of device process and layout.