A Novel Design of DSP/CPLD Digital Logic Laboratory
碩士 === 中原大學 === 電機工程研究所 === 90 === ABSTRACT The objective of this thesis is to implement a DSP-CPLD digital logic design system. Through practical verification and simulation, it is proved that this experimental equipment can improve digital logic circuit teaching, and shorten the time of learning...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15077762222815176928 |