The Analysis of Electrical Characteristics and Roughness Effects of Metal-Oxide-Silicon(MOS) Tunneling Diode

• Main Authors: TANG, CHIH-PANG, 湯治邦
• Other Authors: LIU, CHEEWEE
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/51255572237905961257

碩士 === 國立臺灣大學 === 電機工程學研究所 === 89 === Abstract In this thesis we report the electrical characterization and its roughness effects of metal-oxide- semiconductor (MOS) tunneling diodes. With the device scaling down, thin gate oxide thickness are needed to be 2nm below. But the tunneling current will increase. Therefore, how to make thin and good quality oxide is the most important issue in today’s semiconductor manufacture. Three topics are explored in this thesis. First, we introduce annealing effects on MOSTD (Metal-Oxide-Semiconductor Tunneling Diode). The annealing effects on ultra thin oxide are very different from thick oxide condition. Both annealing time and gas mixture of annealing plays important roles on these devices. The short time annealing in nitrogen ambient improves current-voltage (I-V) characteristics of MOSTD. However, long time annealing in hydrogen or in forming gas induce oxide nearly breakdown and increase the inversion current of these devices. We explain these phenomenons by hydrogen defects and Al spiking. In the last, we discuss the reaction of Al on silicon dioxide after a long time annealing. Second, we talk about capacitance-voltage (C-V) characteristics and technique of MOSTD. Because of ultra thin gate oxide, the C-V curve is very hard to measure due to great large leakage current. We find the capacitance decreases in accumulation region due to this consequence. And we use dual frequency method and parallel circuit model to derived the real capacitance. This model is very easy by using some impedance equivalent theorem. Finally, we also measure C-V profiles about different poly-gate and discuss them. The third is the oxide surface roughness analysis of our MOSTD. Due to UHV bake process, we could create rough oxide surface. And many studies had reported that roughness induces a larger gate current than smooth one. We can see the same results, bur the reasons, which should be responsible for this increase are much different. This is because the gate oxide is too thin. Many surface effects cannot be ignoring. We think that the main reason is the problem of electric field. Our simulation results also support this argument.