The Design and Realization of Digital Calibration in 10-bit 10 MSPS Pipelined ADC
碩士 === 國立臺灣大學 === 電機工程學研究所 === 89 === The goal of this thesis is to understand the calibration in capacitor’s mismatch error for pipelined ADC, one precision multiply-by-2 circuit is made from Switch-Capacitor, the capacitor’s mismatch error will reduce the Differential Nonlinearity(DNL), for increa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59693826365920488412 |