A +3.3V Low Voltage Differential Signaling (LVDS) Transmitter for Flat Panel Display (FPD) Link

• Main Authors: Sung-Yau Yeh, 葉松銚
• Other Authors: Chen-Hsin Lien
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/85797148210018702644

碩士 === 國立清華大學 === 電子工程研究所 === 89 === A Low-Voltage-Differential-Signaling transmitter is implemented in TSMC 0.35 1P4M CMOS process to convert 8 bits of CMOS/TTL data into one LVDS data stream. A phase-locked transmit clock is transmitted in parallel with the data stream over a second LVDS link. During every cycle of the transmit clock, 8 bits of input data are sampled and transmitted. If, for example, a transmit clock frequency of 128MHz (XGA mode can be achieved) is chosen, 8 bits of R/G/B data will be transmitted at a rate of 1Gbps. A PLL embedded is used as a transmit clock that operates under 3.3V of power supplies and at an input frequency range between 20MHz and 128MHz. Thus the LVDS transmitter may be employed in VGA, SVGA, XGA, and SXGA display mode applications. This LVDS transmitter together with a LVDS receiver will be placed between a host graphics controller and a LCD panel controller. The RGB signals from a PC or workstation will be transmitted over the LVDS link and then into a LCD driver.