Performance-Driven Synthesis Using Gate-Labeled Retiming

• Main Authors: Tzu-Chieh Tien, 田子杰
• Other Authors: Youn-Long Lin
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/23366155290810352907

博士 === 國立清華大學 === 資訊工程學系 === 89 === In this dissertation, we study the circuit retiming problem. We utilize a gate-labeling method to enhance retiming efficiency and integrate with other synthesis tasks. We propose a retiming system that links to layout, an approach for simultaneous retiming and placement, and a retiming algorithm that integrates clustering. We formally define the gate labeling behind the retiming algorithm proposed by W.-J. Chen et al. We revise their algorithm, prove its correctness, analyze its complexity, and extend it for area optimization. In the deep sub-micron era, retiming needs accurate interconnect delay. Hence, we implement a retiming system to link layout. This system includes a retiming algorithm that incorporates interconnect delay by utilizing the gate-labeling method, an interconnect delay estimator, and a post-retiming layout refinement procedure. Next, we propose an approach for simultaneous retiming and placement. We embed a retiming procedure which incorporates interconnect delay in a force-directed placement algorithm. The retiming procedure estimates interconnect delay by assuming that each retimed flip-flop will be placed to a force-equilibrium position. Then the placement algorithm places retimed flip-flops to their force-equilibrium positions and reduces the clock period. We solve the problem of performance-optimal clustering with retiming. Previous approach proposed by Pan et al.~can only obtain near-optimal solutions. Our labeling method achieves the optimal clock period. Moreover, we speed up circuit t raversal using FIFO queues. We also show that with similar approach, we can achieve the optimal clock period when integrating retiming with technology mapping or resynthesis. We have run experiments for the retiming system linking to layout, the simultaneous retiming and placement, and the clustering with retiming. The first experiment compares retiming results with and without layout consideration. We observe that our approach becomes more effective as the interconnect delay becomes more dominant. The next experiment compares the simultaneous retiming and placement with the pure placement. The results show that simultaneous retiming and placement produces faster circuits than the pure placement. The last experiment compares our clustering approach with Pan's. Our algorithms not only achieve the optimal clock period but also runs faster than Pan's.