ESD implantations and new diode structures in sub-quarter-micron bulk CMOS technology
碩士 === 國立交通大學 === 電子工程系 === 89 === In this thesis, the influence on ESD robustness with the different ESD implantations and layout design on gate-grounded NMOS (GGNMOS) and gate-VDD PMOS are investigated in a 0.18-µm salicided CMOS technology. A novel diode structure to avoid the formatio...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92121947857244565886 |