Funtional Error Diagnosis for Designs in HDLs

• Main Authors: Tai-Ying Chiang, 江泰盈
• Other Authors: Jing-Yang Jou
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/98332318359494956353

碩士 === 國立交通大學 === 電子工程系 === 89 === Functional mismatches between the register-transfer-level (RTL) HDL simulation and the specification often occur during the design stage. However, the complexity of modern designs is getting higher and higher such that manually tracing the codes to find the bugs becomes more and more difficult. In this thesis, we propose an effective approach for automatic functional error diagnosis, which can handle multiple errors with only one erroneous test case. For the error candidates, we will first eliminate some impossible statements to obtain a smaller set of statements, which is called the error space. Then, we will try to estimate the possibility of being correct for each statement in the error space with some heuristics and display those statements in a prioritized order according to their possibility. It can be very helpful because users are very possible to find their bugs in the first few terms such that the debugging efforts to trace all error candidates can be significantly reduced. Conducting some experiments on several designs, we can show that the size of the error space is indeed small and the true erroneous statements are always displayed in the first few lines with the proposed techniques.