Funtional Error Diagnosis for Designs in HDLs

碩士 === 國立交通大學 === 電子工程系 === 89 === Functional mismatches between the register-transfer-level (RTL) HDL simulation and the specification often occur during the design stage. However, the complexity of modern designs is getting higher and higher such that manually tracing the codes to find...

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Bibliographic Details
Main Authors: Tai-Ying Chiang, 江泰盈
Other Authors: Jing-Yang Jou
Format: Others
Language:en_US
Published: 2001
Online Access:http://ndltd.ncl.edu.tw/handle/98332318359494956353