Design of PLL-Based Frequency Synthesizer for ADC in LCD Monitor
碩士 === 國立交通大學 === 電子工程系 === 89 === This thesis describes the design of a PLL-based frequency synthesizer for ADC in LCD Monitor. It is the interface between internal clock and external clock. It serves to lock the external and internal clock phases to achieve synchronization. It also generates an in...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22664447905148769910 |