Design of Low-Voltage Current-Mode CMOS Sample-and-Hold Circuits
碩士 === 國立中興大學 === 電機工程學系 === 89 === Abstract The low-voltage, current-mode, CMOS, sample-and-hold circuit has been designed in this thesis. The proposed circuit includes a pair of current-mirror circuits with low-voltage operational amplifier, which keeps the input node voltage...
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| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09128543692462876606 |