Design and Fabrication of SiGe Complementary MOS Transistor
碩士 === 義守大學 === 電子工程學系 === 89 === In this thesis, we explore the application of Si/SiGe heterostructres for CMOS transistors operation. The design consists of a strained Si1-xGex quantum well (as the hole channel) and a strained Si quantum well (as the electron channel) on relaxed Si1-yGey well. A...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81796166461680987908 |
| Summary: | 碩士 === 義守大學 === 電子工程學系 === 89 === In this thesis, we explore the application of Si/SiGe heterostructres for CMOS transistors operation. The design consists of a strained Si1-xGex quantum well (as the hole channel) and a strained Si quantum well (as the electron channel) on relaxed Si1-yGey well. A 1-D analytical model is used to simulate the channel charge distribution and the carrier transport characteristics are modeled using 2-D drift-diffusion numerical simulations.
The work in this thesis provides new information on the application of TEOS oxide deposited by low-pressure chemical vapor deposition (LPCVD) to SiGe metal-oxide-semiconductor devices. The electrical properties of LPCVD-deposited SiGe oxide are examined by high/low frequency capacitance–voltage (C-V), current-voltage (I-V) and time dependent dielectric breakdown (TDDB) measurements. The C-V characteristics of poly-gate SiGe MOS capacitors indicate that the fixed charge and interface state densities of the LPCVD-grown SiGe oxide are lower than the results reported in the literature.
Si CMOSFETs with LP-TEOS gate oxide have been successful fabricated and their electrical properties have been fully investigated.
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