CPLD Design and Implementation of a Pipeline FFT Processor
碩士 === 義守大學 === 電子工程學系 === 89 === Based on the Decimation-in-frequency method, the design of FFT pipeline VLSI architecture is proposed in this work. As compared with traditional parallel architecture, the proposed architecture has the advan-tage of reducing the computational complexity....
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/80823302262973626608 |