Research on the Design of Low Voltage CMOS Phase Locked Loops for Clock Generator
碩士 === 中原大學 === 電子工程研究所 === 89 === The aim of this thesis is to design a low voltage CMOS phase locked loop (PLL) for clock generator applications. The charge pump concept has been used in the PLL implementation and the core circuit blocks of the system consist of a phase frequency detect...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99611381305822154332 |