An Input Model for a Semiconductor Final Test Facility

• Main Authors: Chun-Chih Chiu, 邱俊智
• Other Authors: Kung-Jeng Wang
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/20507678072494521241

碩士 === 中原大學 === 工業工程研究所 === 89 === In the semiconductor Industry, most of literatures discussed the input model of wafer fabrication. This thesis discussed the input model of the assembly and final test combined facility. It’s based on the assumption of capacity of final test facility to develop a suitable input model. We use the result to measure system performance from the proposed input model. Base on the test capacity constrained, we use genetic algorithms for find device input optimization solutions. To archive the expected goal of facility, this input model must solve below 3 points: 1.Make the maximum profit both Assembly and Final Test Facility. 2.Make good output performance to satisfy customer demand. 3.Reduce WIP quantity and cycle time. The first part of this thesis is about the background of research and problem defined. The second part is the relevant literature of genetic algorithm. And the latest part is use GA program to find the optimum solution. Finally, we use the result doing the Analysis of Variance to get more evidence to prove this input model is more usefully than the one we use before.