| Summary: | 博士 === 國立中正大學 === 資訊工程研究所 === 89 === In this thesis, we first presents a new test architecture,
called TLS (Tree-LFSR/SR), to more effectively
generate pseudo-exhaustive test patterns for both combinational
and sequential VLSI circuits. Instead of using a single scan chain,
the proposed test architecture routes a scan tree driven by
the LFSR (linear feedback shift register)
to generate all possible input patterns for each output cone.
The new test architecture is able to take advantages of both signal
sharing and signal reuse. The benefits are:
(1) the difficulty of test architecture synthesis can be eased by accelerating
the searching process of appropriate residues, and
(2) the number of XOR gates to satisfy the pseudo-exhaustive
test criterion can be reduced.
The TLS test scheme mainly contains three phases: backbone
generation, tree growing, and XOR-tree generation.
Experimental results obtained by simulating
combinational and sequential benchmark circuits are very encouraging.
Next, to reduce the test time, pseudo-exhaustive testing
inserts some bypass
storage cells (bscs) so that the dependency of each node is within some
predetermined value. Though bsc insertion can reduce the test time,
it may increase circuit delay. For this issue,
our objective is to reduce the
delay penalty of bsc insertion for pseudo-exhaustive testing.
We first propose a tight delay lower bound algorithm which estimates
the minimum circuit delay for each node after bsc insertion.
By understanding how the lower bound algorithm lose optimality,
we then propose a bsc insertion heuristic which tries to insert bscs so
that the final delay is as close to the lower bound as possible.
Our experiments show that the results of our heuristic are either optimal
because they are the same as the delay lower bounds or they are very close
to the optimal solutions.
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