Interconnect Delay Bound Generator for VLSI Physical Design Synthesis
碩士 === 元智大學 === 資訊工程研究所 === 88 === Though the net-length bound driven placement has long been questioned by many designers about its feasibility, it is worth revisiting this approach given that net length bounds can be adapted for the progress of the placement process. In response to an attempt to d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57972351684588043282 |