Optimizing Performance of Dynamic Delayed Micro-pipeline Architecture in Digital Signal Processing

• Main Authors: Jar-shin Yan, 嚴嘉鑫
• Other Authors: Chaio-Jang Hwang
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/93348833768953934762

碩士 === 元智大學 === 資訊工程研究所 === 88 === The hardware architecture is an important technology of the digital signal processing, (as VLIW, pipeline, parellel …etc.) Those technologys improve digital signal processor’s performance greatly. Generally, DSP implementation technology often using the synchronous architecture, but synchronous architecture always brought some issues, like clock skew, drive of fan out, power consumption…and so on. Now we provide a different method to avoids these issue, this method not only avoids synchronous architecture’s issues but also improves the performane of digital signal processing, the method is called ”Dynamic delayed micro-pipeline architecture”. Micro-pipeline is an asynchronous circuit of pipeline, it uses the event signal driving pipeline stages and make its machinism work correctlly, the feature of the micro-pipeline can enhance the performance of DSP chip. In this paper, we add a new concept into the asynchronous micro-pipeline, which is dynamic delay element. This element can select the different delay length of each dynamic delay stage, and saving the waiting time between the pipeline stages, this technique make the micro-pipeline more effecientlly and improves the performance of DSP chip.