Optimizing Performance of Dynamic Delayed Micro-pipeline Architecture in Digital Signal Processing
碩士 === 元智大學 === 資訊工程研究所 === 88 === The hardware architecture is an important technology of the digital signal processing, (as VLIW, pipeline, parellel …etc.) Those technologys improve digital signal processor’s performance greatly. Generally, DSP implementation technology often using the...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93348833768953934762 |