Interconnect-Length Driven Placement with Simultaneous Gate Resizing and Buffer Insertion
碩士 === 元智大學 === 資訊工程研究所 === 88 === Timing-driven physical design approaches have been widely used to reduce the critical path delay of a VLSI circuit. These approaches can be classified as net-weight, net-length or path-delay driven, sometimes accompanied by gate resizing, buffer insertion or wire s...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24570032489834342858 |