| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 88 === In this thesis, the 10-bit nine-stage pipelined analog-digital converter (ADC) is designed. The 1.5b/stage architecture associated digital correction is adopted in this pipelined ADC. The ADC architecture includes eight 1.5-bit stages and one 2-bit stage. The 1.5-bit stage contains two comparators and a switched-capacitor circuit which consists of an operational amplifier, capacitors and switches, and resistor string; the 2-bit stage is a flash ADC. The comparator is composed of a folded-cascode amplifier and current-triggered latch and we used a switched-capacitor circuit to achieve multiple purposes of digital-to-analog converter, subtraction, and amplification. Without absolutely accurate capacitance, a switched-capacitor requires only relatively accurate capacitance and for the CMOS processing technology, it can be fabricated easily. The simulated results show that the converter can operate at 5MHz with the maximum integral nonlinearity error of 1LSB and dissipate 75mW.
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