The Design of CMOS Pipelined Analog-to-Digital Converter
碩士 === 國立臺灣科技大學 === 電子工程系 === 88 === In this thesis, the 10-bit nine-stage pipelined analog-digital converter (ADC) is designed. The 1.5b/stage architecture associated digital correction is adopted in this pipelined ADC. The ADC architecture includes eight 1.5-bit stages and one 2-bit sta...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51270206157213715188 |